The invention relates generally to vertical field effect transistors. More particularly, the invention relates to vertical field effect transistor arrays with enhanced performance.
Planar field effect transistors are common devices in the semiconductor fabrication art. Planar field effect transistors are readily fabricated as complementary doped pairs using self aligned methods that use a gate electrode as a self aligned mask for forming source/drain regions into a semiconductor substrate. Planar field effect transistors have been successfully scaled for several decades to increasingly smaller lateral and transverse linewidth dimensions (i.e., linewidth dimensions that are within a plane of a planar transistor, rather than vertical to the plane of the planar transistor).
A recent trend in field effect transistor design and fabrication that competes with the continued trend in planar field effect transistor device scaling is the design and fabrication of vertical field effect transistor devices. In comparison with a planar field effect transistor device where a gate electrode covers a planar channel within a semiconductor substrate, a vertical field effect transistor device, in a first instance, comprises a semiconductor pillar, a horizontal top region of which and a horizontal region at the base of which typically comprise source/drain regions. A circumference of the pillar and a height of the pillar define a channel area within the semiconductor pillar. A vertical field effect transistor may thus benefit from an offset in scaling in a vertical direction with respect to a horizontal direction (i.e., as a pillar linewidth is scaled to a narrower linewidth dimension a pillar height may be increased to maintain a constant vertical field effect transistor channel area). Such an offset in scaling is not achievable for a planar field effect transistor since scaling of such a planar device occurs in both a lateral planar direction and a transverse planar direction.
While vertical field effect transistor devices thus have advantage in comparison with planar field effect transistor devices, vertical field effect transistor devices are nonetheless not entirely without problems. In particular, vertical field effect transistor devices do not always provide optimal channel properties for use in multiple applications.
Various vertical field effect transistor device structures and methods for fabrication thereof are known in the semiconductor fabrication art.
For example, Takato et al., in “High Performance CMOS Surrounding Gate Transistor (SGT) for Ultra High Density LSIs,” IEEE IEDM 1988, pp. 222-25, teaches a surrounding gate transistor (SGT) with source/drain regions located at a top of a semiconductor pillar and at a floor of a semiconductor substrate adjoining the semiconductor pillar. This particular prior art reference contemplates circuit area reductions of 50% when using the foregoing surrounding gate transistor (SGT) in comparison with a planar transistor when fabricating a circuit.
In addition, Hioki et al., in “An Analysis of Program and Erase Operations for FC-SGT Flash Memory Cells,” 0-7803-6279-9/00, IEEE 2000, pp, 116-18, teaches a floating channel surrounding gate transistor (FC-SGT) that realizes high speed bipolarity program and erase operations. The floating channel surrounding gate transistor (FC-SGT) comprises a semiconductor pillar comprising source/drain regions at a top region and a bottom region of the semiconductor pillar, and separated by a channel region within a central portion of the semiconductor pillar.
Further, Endoh et al., in: (1) “2.4F2 Memory Cell Technology with Stacked-Surrounding Gate Transistor (S-SGT) DRAM,” IEEE Trans. on Electron Devices, 45(8) August 2001, pp. 1599-1603; and (2) “Novel Ultrahigh-Density Flash Memory With a Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell,” IEEE Trans. on Electron Devices, 50(4), April 2003, pp 945-51, each teach the use of a stacked-surrounding gate transistor (S-SGT) in memory cell applications. The stacked-surrounding gate transistor comprises a semiconductor pillar that has a stepped sidewall to accommodate separate components within the memory cell applications.
Still further, Matsuoka, et al, in U.S. Pub. No. 2004/0233769, teaches a semiconductor memory cell and method for fabrication of the semiconductor memory cell. The semiconductor memory cell uses a vertical select transistor configured within the context of a 4F2 structure in order to avoid a large memory cell area.
Finally, Kim, in U.S. Pub. No. 2005/0186740 teaches a vertical field effect transistor structure and a method for fabricating the vertical field effect transistor structure. The vertical memory cell also comprises a 4F2 structure that maximizes semiconductor substrate area utilization.
Semiconductor structure and device dimensions are certain to continue to decrease and, as a result thereof, semiconductor structures that are readily scalable absent compromise in performance characteristics are desirable. To that end, also desirable are vertical field effect transistor devices and arrays such as surrounding gate transistor (SGT) devices and arrays, and methods for fabrication of the devices and arrays, that allow for enhanced flexibility and performance of the vertical field effect transistor devices and arrays.